1. Field of the Invention
The present invention relates to a semiconductor storage apparatus and a data programming method thereof.
2. Description of the Related Art
In recent years, a resistance change memory has attracted attention as a candidate to succeed the flash memory. Here, the resistance change memory includes, in addition to a resistance change memory (ReRAM: Resistive RAM) in a narrow sense in which transition-metal oxide is used as a recording layer and a resistance state thereof is stored in a nonvolatile manner, a phase change memory (PCRAM: Phase Change RAM) in which chalcogenide or the like is used as a recording layer and resistance information of a crystalline state (conductor) and an amorphous state (insulator) thereof is used.
It is known that a variable resistive element of a resistance change memory has two operation modes: one operation mode is called a bipolar type in which a high-resistance state and a low-resistance state are set by switching polarity of an applied voltage; and the other operation mode is called a unipolar type in which a high-resistance state and a low-resistance state are made to be settable by controlling the voltage value and voltage application time without switching polarity of the applied voltage.
The unipolar type is desirable to achieve a high-density memory cell array. This is because when the unipolar type is adopted, a cell array can be formed by piling up a variable resistive element and a rectifying element such as a diode at a crossing portion of a bit line and a word line, without using a transistor. Further, by arranging and laminating such memory cell arrays three-dimensionally, a large capacity can be achieved without increasing a cell array area (see Japanese Patent Application Laid-Open No. 2002-541613).
In order to achieve a cost-effective memory chip by increasing the integration degree of a memory cell array, it is necessary to reduce the number of divisions of the memory cell array and laminate as many cell arrays as possible in a vertical direction. In that case, however, the distance between peripheral circuits and memory cell arrays increases and a wire between bit lines and peripheral circuits may have a large parasitic capacitance. Such a large parasitic capacitance could cause an erroneous write or an erroneous erase operation in memory cells.